1. Field of the Invention
The disclosed embodiments of the present invention relate to a method of scan clock domain allocation and related machine readable media utilizing the method of scan clock domain allocation, and more particularly, to a method for determining the scan clock domain allocation of an integrated circuit and related machine readable media.
2. Description of the Prior Art
A scan test pattern is widely used in an integrated circuit testing flow, wherein the scan test pattern should be used on a testing machine along with a scan clock, and the number of scan clocks is limited to a limited pin number of a chip or a testing machine. Different function clock domains need to be grouped in order to share the same scan clock in a scan test mode; that is, more than one function clock domain would be replaced by the scan clock to become a new scan clock domain. To avoid instantaneous testing power surges, however, more than one scan clock is used and the phases of the scan clocks are staggered. When two function clock domains are asynchronous or have large false paths, grouping the two function clock domains would introduce a large amount of timing violations in scan test mode, resulting in the need to increase area and power consumption in order to fix the timing violations.
Therefore, in a conventional testing flows, scan clock domain allocation usually has to be repeated after the clock tree synthesis, and a preferred result may be obtained after iterative violation fixing several times, or even necessitating a large extra chip area and the use of man power in exchange for a timing solution. This kind of flow and process is time and resource consuming. Thus, there is a need for an innovative design which can group a plurality of function clock domains and allocate the grouped function clock domains into a limited number of scan clock domains efficiently.